| Fast HUB Floating-Point Adder for FPGA | 0 | 0.34 | 2019 |
| HUB Floating Point for Improving FPGA Implementations of DSP Applications. | 1 | 0.36 | 2017 |
| Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. | 5 | 0.54 | 2016 |
| New Formats for Computing with Real-Numbers under Round-to-Nearest | 8 | 0.77 | 2016 |
| Simplified floating-point units for high dynamic range image and video systems | 4 | 0.53 | 2015 |
| Efficient floating-point representation for balanced codes for FPGA devices | 2 | 0.40 | 2013 |
| Multioperand Redundant Adders on FPGAs | 6 | 0.49 | 2013 |
| Decimal online multioperand addition | 0 | 0.34 | 2012 |
| Radix-2 Multioperand and Multiformat Streaming Online Addition | 2 | 0.39 | 2012 |
| Redundant Floating-Point Decimal CORDIC Algorithm | 2 | 0.38 | 2012 |
| High-speed algorithms and architectures for range reduction computation | 0 | 0.34 | 2011 |
| UCORE: Reconfigurable Platform for Educational Purposes | 0 | 0.34 | 2010 |
| Enhanced scaling-free CORDIC | 6 | 0.64 | 2010 |
| Efficient Implementation of Carry-Save Adders in FPGAs | 8 | 0.81 | 2009 |
| Computation of Decimal Transcendental Functions Using the CORDIC Algorithm | 6 | 0.50 | 2009 |
| Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator | 2 | 0.48 | 2009 |
| Pipelined Architecture for Additive Range Reduction | 2 | 0.44 | 2008 |
| A Low-Latency Pipelined 2D and 3D CORDIC Processors | 10 | 0.69 | 2008 |
| SIMD Enhancements for a Hough Transform Implementation | 0 | 0.34 | 2008 |
| Pipelined Range Reduction for Floating Point Numbers | 0 | 0.34 | 2006 |
| Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations | 6 | 0.74 | 2006 |
| Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA | 3 | 0.42 | 2006 |
| SAD computation based on online arithmetic for motion estimation | 13 | 0.87 | 2006 |
| On-line Multioperand Addition Based on On-line Full Adders | 4 | 0.54 | 2005 |
| Low Latency Pipelined Circular CORDIC | 2 | 0.39 | 2005 |
| Evaluation of Elementary Functions Using Multimedia Features | 2 | 0.43 | 2004 |
| CORDIC Processor for Variable-Precision Interval Arithmetic | 10 | 0.64 | 2004 |
| Minimum Sum of Absolute Differences Implementation in a Single FPGA Device | 8 | 1.26 | 2004 |
| Polynomial evaluation on multimedia processors | 6 | 0.62 | 2002 |
| A Hardware Algorithm for Variable-Precision Logarithm | 5 | 0.46 | 2000 |
| MMX-Like Architecture Extension to Support the Rotation Operation | 1 | 0.37 | 2000 |
| Arithmetic Unit for the Computation of Interval Elementary Functions | 1 | 0.36 | 1999 |
| Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm | 5 | 0.50 | 1999 |
| Parallel Compensation of Scale Factor for the CORDIC Algorithm | 13 | 0.90 | 1998 |
| Low latency word serial CORDIC | 1 | 0.37 | 1997 |
| High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm | 33 | 1.84 | 1997 |
| Cordic based parallel/pipelined architecture for the Hough transform | 19 | 1.30 | 1996 |
| Radix-4 Vectoring CORDIC Algorithm and Architectures | 6 | 0.54 | 1996 |
| High Radix Cordic Rotation Based on Selection by Rounding | 12 | 0.85 | 1996 |
| Redundant CORDIC Rotator Based on Parallel Prediction | 5 | 0.70 | 1995 |
