Name
Abstract | ||
|---|---|---|
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable heterogeneous CMP and its performance and power evaluation with the OSCAR (Optimally SCheduled Advanced multiprocessoR) parallelizing compiler[1]. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.5555/1299042.1299091 | Ieice Transactions |
Keywords | Field | DocType |
operating frequency,compiler controllable heterogeneous cmp,power evaluation,higher performance,chip multi-processors,parallelizing compiler,processor element,optimally scheduled advanced multiprocessor,power consumption,power-aware compiler controllable chip,power control,functional unit,real time | Computer science,Power control,Parallel computing,Chip,Compiler,Multiprocessing,Power electronics,Multi-core processor,Clock rate,Low-power electronics,Embedded system | Conference |
Volume | Issue | ISSN |
91-C | 4 | 0916-8524 |
ISBN | Citations | PageRank |
978-0-7695-2944-8 | 2 | 0.61 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroaki Shikano | 1 | 28 | 4.90 |
| Jun Shirako | 2 | 433 | 34.56 |
| Yasutaka Wada | 3 | 72 | 11.19 |
| Keiji Kimura | 4 | 120 | 23.20 |
| Hironori Kasahara | 5 | 285 | 44.35 |