Name
Abstract | ||
|---|---|---|
In this paper the inclusion of hardware constraints into the design of massively parallel processor arrays is considered. We propose an algorithm which determines an optimal scheduling function as well as the selection of components which have to be implemented in one processor of a processor array. The arising optimization problem is formulated as an integer linear program which also takes the necessary chip area of a hardware implementation into consideration. Thereby we assume that an allocation function is given and that a partitioning of the processor array is required to match a limited chip area in silicon. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/ASAP.1997.606826 | ASAP |
Keywords | Field | DocType |
integer linear program,allocation function,processor arrays,hardware constraint,optimization problem,limited chip area,necessary chip area,hardware implementation,processor array,parallel processor array,processor functionality,optimal scheduling function,process design,high level synthesis,integer programming,algorithm design and analysis,parallel processing,chip,scheduling algorithm,hardware,difference equations,linear programming,silicon | Pipeline burst cache,Network processor,Application-specific instruction-set processor,Processor array,Computer science,Massively parallel,High-level synthesis,Parallel computing,Real-time computing,Integer programming,Processor affinity | Conference |
ISSN | ISBN | Citations |
1063-6862 | 0-8186-7958-1 | 6 |
PageRank | References | Authors |
0.59 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Fimmel | 1 | 6 | 0.59 |
| Renate Merker | 2 | 159 | 20.59 |