Name
Abstract | ||
|---|---|---|
We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1023/A:1015413306258 | VLSI Signal Processing |
Keywords | Field | DocType |
interface synthesis,logic circuit,embedded systems | Logic gate,Computer science,Parallel computing,Interface circuits,Real-time computing,Application-specific integrated circuit,Dynamic demand,Encoding (memory) | Journal |
Volume | Issue | ISSN |
31 | 3 | 0922-5773 |
Citations | PageRank | References |
0 | 0.34 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ki-seok Chung | 1 | 189 | 18.76 |
| Rajesh K. Gupta | 2 | 4570 | 390.84 |
| Taewhan Kim | 3 | 1087 | 113.31 |
| C. L. Liu | 4 | 6191 | 970.79 |