Paper Info
Title
Static analysis of processor stall cycle aggregation
Abstract
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the processor is switched to low-power mode in it. We extend the previous proposed approach in two dimensions. i) We develop static analysis for the PICA technique and present optimum parameters for five common types of loops based on steady-state analysis. ii) We show that software only control is unable to guarantee its correctness in a varying runtime environment, potentially causing deadlocks. We enhance the robustness of PICA with minimal hardware extension, ensuring correct execution for any loops and parameters, which greatly facilitates exploration based parameter optimization. The combined use of our static analysis and exploration based fine-tuning makes the PICA technique applicable, to any memory-bound loop, with energy reduction. We validate our analytical models against simulation based optimization and also show through our experiments on embedded application benchmarks, that our technique can be applied to a wide range of loops with average 20% energy reductions compared to executions without PICA.
Year
DOI
Venue
2008
10.1145/1450135.1450143
CODES+ISSS
Keywords
Field
DocType
energy reduction,parameter optimization,low power execution,promising approach,correct execution,cycle aggregation,previous proposed approach,facilitates exploration,steady-state analysis,static analysis,pica technique,two dimensions,embedded systems,steady state analysis,embedded system
Idle,Computer science,Stall (fluid mechanics),Parallel computing,Static analysis,Simulation-based optimization,Correctness,Deadlock,Robustness (computer science),Real-time computing,Software
Conference
Citations 
PageRank 
References 
2
0.40
11
Authors
2
Name
Order
Citations
PageRank
Jongeun Lee142933.71
Aviral Shrivastava281268.67