Name
Title | ||
|---|---|---|
Scan Chain Ordering To Reduce Test Data For Bist-Aided Scan Test Using Compatible Scan Flip-Flops |
Abstract | ||
|---|---|---|
In this paper, the scan chain ordering method for BIST-aided scan test for reducing test data and test application time is proposed. In this work. we utilize the simple LFSR without a phase shifter as PRPG and configure scan chains using the compatible set of flip-flops with considering, the correlations among flip-flops in an LFSR. The method can reduce the number of inverter codes required for inverting, the bits in PRPG partterns that conflict with ATPG patterns. The experimental results for some benchmark circuits are shown to present the feasibility of our test method. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transinf.E93.D.10 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
BIST-aided scan test, scan chain ordering, test data reduction, compatible flip-flops, test pattern generation | Automatic test pattern generation,Test method,Shift register,Sequential logic,Computer science,Scan chain,Algorithm,Test data,Test compression,Built-in self-test | Journal |
Volume | Issue | ISSN |
E93D | 1 | 1745-1361 |
Citations | PageRank | References |
1 | 0.36 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Masayuki Yamamoto | 2 | 1 | 0.36 |
| Masaki Hashizume | 3 | 98 | 27.83 |