Abstract | ||
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Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns. |
Year | DOI | Venue |
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2011 | 10.1109/IOLTS.2011.5993816 | On-Line Testing Symposium |
Keywords | Field | DocType |
static random access memory,ternary content addressable memory,read-only memory,power buffer-zones,generic bist architecture,test algorithm,existing bist architecture,important cam specific feature,quarter word,single-port binary,finite element method,tcam,computer architecture,rom,sram,content addressable memory,fault,cam,read only memory,finite element methods,computer aided manufacturing | Computer-aided manufacturing,Architecture,Computer architecture,Content-addressable memory,Computer science,Static random-access memory,Content-addressable storage,Binary number,Random access,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1942-9398 | 978-1-4577-1053-7 | 6 |
PageRank | References | Authors |
0.64 | 7 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
H. Grigoryan | 1 | 6 | 0.64 |
G. Harutyunyan | 2 | 6 | 0.64 |
S. Shoukourian | 3 | 6 | 0.98 |
Valery A. Vardanian | 4 | 77 | 9.70 |
Y. Zorian | 5 | 499 | 47.97 |