Paper Info
Title
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors
Abstract
In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from [email protected] to [email protected]) for the proposed SRAM array.
Year
DOI
Venue
2011
10.1109/ISLPED.2011.5993654
ISLPED
Keywords
Field
DocType
write-back operation,conventional write-back scheme,minimal limitation,sram architecture,dual port advantage,column selection,proposed local write-back scheme,proposed sram array,dvfs-enabled processor,multi-port operation,proposed cache,wide-range dvfs,decoding,transistors,cache memory
Architecture,Port (computer networking),Computer architecture,Tag RAM,CPU cache,Computer science,Cache,Real-time computing,Static random-access memory,Decoding methods,Transistor
Conference
ISBN
Citations 
PageRank 
978-1-61284-660-6
8
1.00
References 
Authors
5
6
Name
Order
Citations
PageRank
Sang Phill Park153531.56
Soo Youn Kim281.67
Dongsoo Lee323330.63
Jae-Joon Kim427537.46
W. Paul Griffin581.00
Kaushik Roy61531142.83