Name
Abstract | ||
|---|---|---|
Information on false paths is useful for design and test. Since identification of false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, the correspondence has been established only by some restricted logic synthesis. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DELTA.2010.23 | Ho Chi Minh City |
Keywords | Field | DocType |
test futileness,false path,gate level,specific logic synthesis,high-level design information,corresponding gate level path,enabling false path identification,restricted logic synthesis,register transfer level,rtl false path,network synthesis,logic gates,logic synthesis,logic design | Logic synthesis,Functional equivalence,Design information,Logic gate,Computer science,Network synthesis filters,Electronic engineering,False path,If and only if,Register-transfer level | Conference |
ISBN | Citations | PageRank |
978-1-4244-6026-7 | 1 | 0.38 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroshi Iwata | 1 | 1 | 0.38 |
| Satoshi Ohtake | 2 | 135 | 21.62 |
| Hideo Fujiwara | 3 | 184 | 20.31 |