Name
Abstract | ||
|---|---|---|
In the advanced Audio Video coding Standard (AVS), many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, direct mode matching, variable block-sizes etc. However, these features enormously increase the computational complexity and the memory bandwidth requirement and make the traditional MV predictor more complicated. This paper proposes an efficient MV predictor architecture for both AVS and MPEG-2 decoder. The proposed architecture exploits the parallelism to accelerate the speed of operations and uses the dedicated design to optimize the memory access. In addition, it can reuse the on-chip buffer to support the MV error-resilience for MPEG-2 decoding. The design has been described in Verilog HDL and synthesized using 0.18μm CMOS cells library by Design Compiler. The circuit costs about 62k logic gates when the working frequency is set to 148.5MHz. This design can support the real-time MV predictor of HDTV 1080i video decoding for both AVS and MPEG-2. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/11922162_49 | PCM |
Keywords | Field | DocType |
real time,memory bandwidth,chip,logic gate,computational complexity | Memory bandwidth,Computer science,Motion compensation,Decoding methods,Verilog,Vector processor,Computer hardware,Motion vector,Hardware description language,MPEG-2,Distributed computing,Embedded system | Conference |
Volume | Issue | ISSN |
4261 LNCS | null | 0302-9743 |
ISBN | Citations | PageRank |
3-540-48766-2 | 5 | 0.52 |
References | Authors | |
2 | 5 | |