Name
Title | ||
|---|---|---|
Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator |
Abstract | ||
|---|---|---|
In this paper we present some architectures to deal with fast convolution computation based on carry save adders which are intended to be specifically implemented on FPGAs. Carry-save adders are not frequent in FPGA implementations since FPGA has a fast carry propagation path. In this paper we prove that it is possible to use carry-save arithmetic in a efficient way on FPGA for convolution operation. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carry-propagate additions using the same hardware. This lead to an efficient combined CSA-CPA architecture with fast computation and optimizing the hardware cost. Experimental results for different word lengths are presented to validate our proposal. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICECS.2009.5410903 | Yasmine Hammamet |
Keywords | Field | DocType |
adders,carry logic,field programmable gate arrays,FPGA,carry save adders,carry-propagate additions,carry-save additions,carry-save arithmetic,combined CSA-CPA accumulator,fast convolution computation | Digital signal processing,Adder,Convolution,Computer science,Parallel computing,Field-programmable gate array,Electronic engineering,Computer hardware,Carry propagation,Fpga implementations,Accumulator (structured product),Computation | Conference |
ISBN | Citations | PageRank |
978-1-4244-5091-6 | 2 | 0.48 |
References | Authors | |
5 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carlos D. Moreno | 1 | 2 | 1.16 |
| Francisco J. Quiles | 2 | 438 | 41.67 |
| Manuel Ortiz | 3 | 12 | 3.23 |
| María Brox | 4 | 25 | 4.54 |
| Javier Hormigo | 5 | 113 | 19.45 |
| Julio Villalba | 6 | 219 | 23.56 |
| Emilio L. Zapata | 7 | 811 | 100.36 |