Name
Abstract | ||
|---|---|---|
The leakage power consumption in deep sub-100nmCMOS systems is projected to become a significant part ofthe total power dissipation. Although the dual Vt CMOSprocess helps reduce the subthreshold leakage current indomino circuits, the gate leakage problem poses asignificant design challenge. We propose two new circuittechniques to suppress both subthreshold leakage currentand gate leakage current in domino circuits. In standbymode, subthrshold leakage current is suppressed byusinging dual Vt devices in the two proposed circuits. Theproposed circuits generate low inputs and low outputs tosuppress gate leakage current in the NMOS logic tree instandby mode. Simulation results based on 45nm BSIM4models show that 32-bit adders using the two proposedcircuits can reduce the total standby leakage by 83.2%and 93.2%, respectively, compared with the adder usingsingle Vt domino circuits. Proposed adders have 7%active power overhead to achieve the same speed as singleVt domino adder and the area penalty is minimal withcareful layout. |
Year | Venue | Keywords |
|---|---|---|
2004 | VLSI Design | subthrshold leakage current,gate leakage problem,Vt domino circuit,total standby leakage,subthreshold leakage current indomino,active power overhead,leakage power consumption,tosuppress gate leakage,Leakage-Proof Domino Circuit Design,Deep Sub-100nm Technologies,domino circuit,subthreshold leakage currentand gate |
DocType | ISBN | Citations |
Conference | 0-7695-2072-3 | 11 |
PageRank | References | Authors |
0.96 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ge Yang | 1 | 20 | 2.16 |
| Zhongda Wang | 2 | 20 | 1.82 |
| Sung-Mo Steve Kang | 3 | 1198 | 213.14 |