Name
Title | ||
|---|---|---|
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. |
Abstract | ||
|---|---|---|
This study presents a row-linear feedback shift register-column (RLC) masking technique that is capable of handling many unknowns in the test responses. The proposed technique takes advantage that most unknowns are locally clustered after the test compactor. With three novel masking mechanisms [direct row, direct column and linear feedback shift register (LFSR) column masking], RLC masks all unknowns in test responses using a very short LFSR. Experiments on a real design show that the proposed technique is able to mask up to 7.38% unknowns with only 0.61% fault coverage loss. By providing a very high test response compaction ratio, RLC masking technique enables massive parallel testing of many-core system chips. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1049/iet-cdt.2010.0041 | IET Computers & Digital Techniques |
Keywords | Field | DocType |
integrated circuit testing,microprocessor chips,shift registers,RLC masking technique,direct column masking mechanisms,direct row masking mechanisms,many-core system chips,parallel testing,row-linear feedback shift register-column x-masking technique,simultaneous testing | Shift register,Linear feedback shift register,Fault coverage,Masking (art),Computer science,Real-time computing,Computer hardware,RLC circuit | Journal |
Volume | Issue | ISSN |
5 | 4 | 1751-8601 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| W.-C. Wang | 1 | 0 | 0.34 |
| C.-Y. Hsu | 2 | 0 | 0.34 |
| James Chien-Mo Li | 3 | 187 | 27.16 |
| Y.-C. Sung | 4 | 0 | 0.34 |
| A. Rao | 5 | 0 | 0.34 |
| L.-T. Wang | 6 | 1 | 2.39 |