Paper Info
Title
A high-performance area-efficient AES cipher on a many-core platform
Abstract
This paper presents the design and software implementation of a high-performance area-efficient Advanced Encryption Standard (AES) cipher on a many-core platform. A preliminary cipher design is partitioned and mapped to an array of 70 small processors, and offers a throughput of 16.625 clock cycles per byte. The usage of instruction and data memory, and the workload of each processor are characterized for further optimization. Through workload balancing and processor fusion, the throughput of the cipher is increased by 43% to 9.5 clock cycles per byte, while the number of processors utilized is reduced to 59, which is only 10.03 mm2 in a 65 nm fine-grained many-core system. In comparison with published AES implementations on general purpose processors, our design has 3.6-10.7 times higher throughput per area. Moreover, the presented design shows 1.5 times higher throughput than the TI DSP C6201 and 3.4 times higher throughput per area than the GeForce 8800 GTX.
Year
DOI
Venue
2011
10.1109/ACSSC.2011.6190389
ACSCC
Keywords
DocType
ISSN
parallel processing,geforce 8800 gtx,data memory,workload balancing,high performance area-efficient aes cipher,microprocessor chips,cryptography,size 65 nm,advanced encryption standard (aes),processor fusion,fine-grained many-core system,resource allocation,parallel mapping,multiprocessing systems,clocks,many-core processor,clock cycles,processor workload,instruction memory,asynchronous array of simple processors (asap),ti dsp c6201,high-performance area-efficient advanced encryption standard cipher,advanced encryption standard
Conference
1058-6393
ISBN
Citations 
PageRank 
978-1-4673-0321-7
0
0.34
References 
Authors
4
2
Name
Order
Citations
PageRank
Bin Liu1128168.98
Bevan M. Baas229527.78