Abstract | ||
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This paper presents a Design for Testability (DFT) toolcalled ACT (Asynchronous Circuit Testing) which uses apartial scan technique to make macro-module based self-timedcircuits testable. The ACT tool is the first of its kindfor testing macro-module based self-timed circuits. ACTmodifies designs automatically to incorporate partial scanand provides a complete path from schematic capture tophysical layout. It also has a test generation system to generatevectors for the testable design and to compute faultcoverage of the generated tests. The test generation systemincludes a module for doing critical hazard free test generationusing a new 6-valued algebra. ACT has been builtaround commercial tools from Viewlogic and Cascade. AViewlogic schematic is used as the design entry point andCascade tools are used for technology mapping. |
Year | DOI | Venue |
---|---|---|
1997 | 10.1109/TEST.1997.639697 | ITC |
Keywords | Field | DocType |
act tool,design entry point andcascade,test generation system,testable design,aviewlogic schematic,dft tool,test generation,self-timed circuits,kindfor testing macro-module,toolcalled act,free test,self-timedcircuits testable,system testing,design for testability,fault coverage,automatic test equipment,act,business,cascade,modules,asynchronous circuit,fault model,protocols | Design for testing,Fault coverage,System testing,Computer science,Automatic test equipment,Schematic capture,Schematic,Electronic engineering,Real-time computing,Computer engineering,Fault model,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-4209-7 | 0 |
PageRank | References | Authors |
0.34 | 16 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Ajay Khoche | 1 | 142 | 11.58 |
Erik Brunvand | 2 | 509 | 66.09 |