Name
Abstract | ||
|---|---|---|
It is well known that a large fraction of variables are short-lived. This paper proposes a novel approach to exploiting this fact to reduce the register pressure for pipelined processors with data-forwarding network. The idea is that the compiler can allocate virtual registers (i.e., place holders to identify dependences among instructions) to short-lived variables, which do not need to be stored to physical storage locations. As a result, real registers (i.e., physically existed registers) can be reserved for long-lived variables for mitigating the register pressure and decreasing the register spills, leading to performance improvement. In this paper, we develop the architectural and compiler support for exploiting virtual registers for statically scheduled processors. Our experimental results show that virtual registers are very effective at reducing the register spills, which, in many cases, can achieve the performance close to the processor with twice number of real registers. Our results also indicate that, for some applications, using 24 virtual, in addition to 8 real registers, can attain even higher performance than that of 16 real without any virtual registers. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1328195.1328198 | TACO |
Keywords | Field | DocType |
real register,higher performance,virtual register,register pressure,register spill,compiler support,performance close,data-forwarding network,performance improvement,register allocation,register file,short-lived variables,short-lived variable,data forwarding | x86 debug register,Register allocation,Computer science,Parallel computing,Control register,Base and bounds,Real-time computing,Register window,Memory type range register,Register renaming,Processor register,Computer hardware | Journal |
Volume | Issue | ISSN |
4 | 4 | 1544-3566 |
Citations | PageRank | References |
7 | 0.44 | 13 |
Authors | ||
2 | ||