Paper Info
Title
Reducing False Transactional Conflicts with Speculative Sub-Blocking State -- An Empirical Study for ASF Transactional Memory System
Abstract
Conflict detection and resolution are among the most fundamental issues in transactional memory systems. Hardware transactional memory (HTM) systems such as AMD's Advanced Synchronization Facility (ASF) employ inherent cache coherence protocol messages to perform conflict detection among transactions. Such an implementation has the advantage of design simplicity, nonetheless, it also generates false transactional conflicts due to false sharing within cache lines, unnecessarily reducing the overall performance. In this work, we first investigated the behavior of false transactional conflicts under the AMD's ASF system. It is found that false conflicts showed rather stable pattern within each cache line that subsequently inspired our false transactional conflict reduction technique using our proposed speculative sub-blocking state. By adding an extra speculative state for each cache line's sub-block, we can maintain conflict detection at the granularity of sub-blocks while keeping the original cache coherence protocol intact. The overall design is simple and highly implementable for achieving a high-efficiency HTM system with minimum impact in hardware. We evaluated our proposed technique using PTLsim-ASF and compared it with a baseline ASF HTM system and an ideal system with no false transactional conflict. Our results showed that the proposed lightweight technique can avoid false conflicts effectively and efficiently. With four sub-blocks in a cache line, our technique can eliminate 56.4% false transactional conflicts and 31.3% of all transactional conflicts on average, which approaches the performance of an ideal system.
Year
DOI
Venue
2013
10.1109/IPDPSW.2013.113
IPDPS Workshops
Keywords
Field
DocType
asf transactional memory,speculative sub-blocking state,cache line,false conflict,false transactional conflict,false sharing,false transactional conflict reduction,empirical study,hardware transactional memory,false transactional conflicts,transactional conflict,conflict detection,ideal system,transactional memory system,concurrency control,synchronisation,data structures,protocols,transactional memory,coherence,genomics,benchmark testing,microarchitecture,conflict resolution,hardware,parallel programming,bioinformatics
Advanced Synchronization Facility,Concurrency control,CPU cache,Cache,Computer science,False sharing,Transactional memory,Transactional leadership,Cache coherence,Distributed computing
Conference
Citations 
PageRank 
References 
0
0.34
9
Authors
2
Name
Order
Citations
PageRank
Lifeng Nai100.34
Hsien-Hsin Sean Lee21657102.66