| ACT: designing sustainable computer systems with an architectural carbon modeling tool | 0 | 0.34 | 2022 |
| SecNDP: Secure Near-Data Processing with Untrusted Memory | 1 | 0.34 | 2022 |
| Hercules: Heterogeneity-Aware Inference Serving for At-Scale Personalized Recommendation | 0 | 0.34 | 2022 |
| Chasing Carbon: The Elusive Environmental Footprint of Computing | 1 | 0.48 | 2021 |
| Special Issue on Commercial Products 2021 | 0 | 0.34 | 2021 |
| RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing | 19 | 0.83 | 2020 |
| DeepRecSys: A System for Optimizing End-To-End At-scale Neural Recommendation Inference | 12 | 0.62 | 2020 |
| The Architectural Implications of Facebook's DNN-Based Personalized Recommendation | 4 | 0.44 | 2020 |
| The Architectural Implications of Facebook's DNN-based Personalized Recommendation. | 6 | 0.41 | 2019 |
| COMPSAC 2015 Plenary Panel on "Rebooting Computing" | 0 | 0.34 | 2015 |
| ATAC: Ambient Temperature-Aware Capping for Power Efficient Datacenters | 2 | 0.37 | 2014 |
| TBPoint: Reducing Simulation Time for Large-Scale GPGPU Kernels | 5 | 0.42 | 2014 |
| Cache-conscious graph collaborative filtering on multi-socket multicore systems | 2 | 0.38 | 2014 |
| Pragmatic integration of an SRAM row cache in heterogeneous 3-D DRAM architecture using TSV | 10 | 0.53 | 2013 |
| Reducing False Transactional Conflicts with Speculative Sub-Blocking State -- An Empirical Study for ASF Transactional Memory System | 0 | 0.34 | 2013 |
| Tri-level-cell phase change memory: toward an efficient and reliable memory system | 46 | 1.33 | 2013 |
| 3D-MAPS: 3D Massively parallel processor with stacked memory | 70 | 2.73 | 2012 |
| Migration energy-aware workload consolidation in enterprise clouds | 1 | 0.35 | 2012 |
| Global Built-In Self-Repair for 3D memories with redundancy sharing and parallel testing. | 9 | 0.54 | 2011 |
| Symbiotic Scheduling for Shared Caches in Multi-core Systems Using Memory Footprint Signature | 2 | 0.39 | 2011 |
| Designing 3D test wrappers for pre-bond and post-bond test of 3D embedded cores | 2 | 0.40 | 2011 |
| Data Prefetching by Exploiting Global and Local Access Patterns. | 2 | 0.37 | 2011 |
| Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation | 2 | 0.38 | 2011 |
| Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping | 121 | 5.48 | 2010 |
| A low-cost memory remapping scheme for address bus protection | 1 | 0.40 | 2010 |
| Architecture/OS Support for Embedded Multi-core Systems | 0 | 0.34 | 2010 |
| SAFER: Stuck-At-Fault Error Recovery for Memories | 55 | 2.38 | 2010 |
| Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching | 1 | 0.35 | 2010 |
| Test Challenges for 3D Integrated Circuits | 137 | 6.24 | 2009 |
| Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches | 19 | 0.79 | 2009 |
| High Performance Non-blocking Switch Design in 3D Die-Stacking Technology | 4 | 0.52 | 2009 |
| Thermal optimization in multi-granularity multi-core floorplanning | 9 | 0.57 | 2009 |
| Testing Circuit-Partitioned 3D IC Designs | 18 | 1.08 | 2009 |
| Pre-bond testable low-power clock tree design for 3D stacked ICs | 31 | 2.28 | 2009 |
| PROPHET: goal-oriented provisioning for highly tunable multicore processors in cloud computing | 2 | 0.41 | 2009 |
| Total recall: a debugging framework for GPUs | 1 | 0.36 | 2008 |
| Kicking the tires of software transactional memory: why the going gets tough | 40 | 1.58 | 2008 |
| SHARK: Architectural support for autonomic protection against stealth by rootkit exploits | 5 | 0.60 | 2008 |
| POD: A 3D-Integrated Broad-Purpose Acceleration Layer | 8 | 1.35 | 2008 |
| Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era | 122 | 6.28 | 2008 |
| Adaptive transaction scheduling for transactional memory systems | 99 | 2.57 | 2008 |
| Improving TLB energy for java applications on JVM | 1 | 0.36 | 2008 |
| DLL-conscious instruction fetch optimization for SMT processors | 1 | 0.36 | 2008 |
| Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs | 132 | 6.49 | 2007 |
| Reducing Cache Pollution via Dynamic Data Prefetch Filtering | 21 | 1.06 | 2007 |
| A scanisland based design enabling prebond testability in die-stacked microprocessors. | 57 | 3.47 | 2007 |
| Optimizing Katsevich image reconstruction algorithm on multicore processors | 1 | 0.38 | 2007 |
| Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis | 6 | 1.89 | 2007 |
| Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs | 26 | 1.44 | 2007 |
| Accelerating memory decryption and authentication with frequent value prediction | 3 | 0.40 | 2007 |
