Name
Abstract | ||
|---|---|---|
A fast pipeline technique using single-phase, edge-triggered, ratioed, high-speed logic flip-flops and D flip-flops is introduced and analyzed. The circuits achieve high speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. Also it is suitable for realizing high-speed synchronous counters. A divide-by-128/129 and 64/65 dual-modulus prescaler using the proposed flip-flops is measured in 0.8 μm CMOS technology with the operating clock frequency reaching as high as 1.8 GHz |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/4.720406 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
fast pipeline technique,index terms— cmos integrated circuits,capacitive load reduction,high-speed dual-modulus prescaler,high-speed synchronous counters,d flip-flops,prescalers,cmos technology,high-speed circuits,cmos logic circuits,1.8 ghz,single-phase edge-triggered flip-flops,prescaler.,flip-flops,0.8 micron,dynamic flip-flops,pipeline processing,cmos integrated circuits,indexing terms,logic circuits,pipelines | Journal | 33 |
Issue | ISSN | Citations |
10 | 0018-9200 | 27 |
PageRank | References | Authors |
3.70 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Guang-Kaai Dehng | 2 | 87 | 17.17 |
| June-Ming Hsu | 3 | 71 | 12.17 |
| Shen-Iuan Liu | 4 | 1378 | 200.41 |