Name
Title | ||
|---|---|---|
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction |
Abstract | ||
|---|---|---|
Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14脳 reduction in test data volume and 98% test power reduction can be obtained simultaneously. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/s10836-007-5053-z | J. Electronic Testing |
Keywords | Field | DocType |
DfT,Scan,Low power testing,Test data compression | Automatic test pattern generation,Wafer,Computer science,Electronic engineering,Test data compression,Test data,Electronic circuit,Test compression,Test power,Encoding (memory) | Journal |
Volume | Issue | ISSN |
24 | 4 | 0923-8174 |
Citations | PageRank | References |
9 | 0.65 | 16 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. Badereddine | 1 | 18 | 2.98 |
| Z. Wang | 2 | 9 | 0.65 |
| P. Girard | 3 | 478 | 41.91 |
| K Chakrabarty | 4 | 8173 | 636.14 |
| A. Virazel | 5 | 169 | 23.25 |
| S. Pravossoudovitch | 6 | 689 | 54.12 |
| C. Landrault | 7 | 9 | 0.65 |