Name
Abstract | ||
|---|---|---|
This paper presents an efficient technique for code compression. In our work, a sequence of instructions that occurs repeatedly in an application will be compressed to reduce its code size. During compression, each instruction is first divided into the operation part and the register part, and then only the operation part is compressed. The compression information is stored in the instruction table, the register bank, and the index table. For reducing the run-time overhead, we propose an instruction prefetching mechanism to speed the decompression. Our work is performed with SPEC 2000, DSPstone, Mediabench, and MPEG4 benchmarks on the basis of the ARM instruction set. It is proved to be quite effective for media and other applications. The experimental results show that our work can achieve a code size reduction of 33% on average and a low overhead in the process of decompression at run time for these benchmarks. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1007/s11227-006-0021-4 | The Journal of Supercomputing |
Keywords | Field | DocType |
Code compression,Decompression,Repeated instruction sequence,Instruction prefetching,Index table,Instruction table,Register bank | Program optimization,ARM architecture,Instruction register,Supercomputer,Computer science,Parallel computing,Data compression,Spec#,Self-modifying code,Code (cryptography) | Journal |
Volume | Issue | ISSN |
40 | 3 | 0920-8542 |
Citations | PageRank | References |
2 | 0.37 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shao-Yang Wang | 1 | 3 | 0.78 |
| Rong-Guey Chang | 2 | 99 | 14.70 |