Rong-Guey Chang - Citegraph

Author Info

Name	Affiliation	Papers
RONG-GUEY CHANG	Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi 621, Taiwan	34
Collaborators	Citations	PageRank
41	99	14.70
Referers	Referees	References
167	782	365

Search Limit

100782

Publications (34 rows)

Collaborators (41 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Chinese story generation of sentence format control based on multi-channel word embedding and novel data format	0	0.34	2022
Chinese Story Generation with FastText Transformer Network	0	0.34	2019
A virtualization approach to develop middleware for ubiquitous high performance computing	0	0.34	2015
A Cyber Physical System with GPU for CNC Applications	0	0.34	2015
A virtualisation simulation environment for data centre.	0	0.34	2015
A priority scheduling for TM pathologies	1	0.35	2015
Power-aware code scheduling assisted with power gating and DVS	2	0.35	2014
Dynamic Voltage and Frequency Scaling Optimization for Multicore Architectures.	0	0.34	2014
Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture.	0	0.34	2014
Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization	19	0.98	2013
Thermal-Aware Scheduling Collaborating with OS and Architecture	0	0.34	2013
DCSim: Design Analysis on Virtualization Data Center	1	0.36	2012
Multi-level simultaneous multithreading scheduling to reduce the temperature of register files	0	0.34	2012
Compiler Optimization to Reduce Cache Power with Victim Cache	1	0.37	2012
Inline Emulation for Paravirtualization Environment on Embedded Systems	1	0.48	2011
Wireless Smooth Data Streaming on Application Layer	1	0.38	2011
Compiler support for concurrency synchronization	0	0.34	2011
Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist	6	0.57	2011
Trading Conditional Execution for More Registers on ARM Processors	1	0.38	2010
DisIRer: Converting a retargetable compiler into a multiplatform binary translator	9	0.49	2010
Wide dynamic-range sigma-delta modulator with adaptive feed-forward coefficients.	0	0.34	2010
Profile-based dynamic pipeline scaling	0	0.34	2009
A Portable and Efficient User Dispatching Mechanism for Multicore Systems	2	0.41	2009
Code size reduction by compressing repeated instruction sequences	2	0.37	2007
Optimizing code size for embedded real-time applications	1	0.41	2006
Power-Aware Instruction Scheduling	0	0.34	2006
Development of architecture and software technologies in high-performance low-power SoC design	0	0.34	2005
Support and optimization for parallel sparse programs with array intrinsics of Fortran 90	2	0.37	2004
Parallel Sparse Supports for Array Intrinsic Functions of Fortran 90	12	0.72	2001
Probabilistic inference schemes for sparsity structures of Fortran 90 array intrinsics	6	0.54	2001
Compiler Optimizations for Parallel Sparse Programs with Array Intrinsics of Fortran 90	7	0.55	1999
Efficient support of parallel sparse computation for array intrinsic functions of Fortran 90	9	0.61	1998
Towards Automatic Support Of Parallel Sparse Computation In Java With Continuous Compilation	9	0.73	1997
Sampling and Analytical Techniques for Data Distribution of Parallel Sparse Computation	7	0.55	1997