Name
Abstract | ||
|---|---|---|
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271574 | ISCAS |
Keywords | Field | DocType |
synchronization,cmos integrated circuits,jitter | Synchronization,Operating frequency,Dissipation,Computer science,Electronic engineering,Chip,CMOS,Jitter | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-0218-0 | 3 |
PageRank | References | Authors |
0.40 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ai-Jia Chuang | 1 | 3 | 0.40 |
| Yu Lee | 2 | 11 | 3.21 |
| Ching-Yuan Yang | 3 | 227 | 36.15 |