Name
Abstract | ||
|---|---|---|
Because of continued advancements in process technology, three-dimensional (3D) integration with stacked chips is emerging as a promising solution to meet the challenges of high-performance, differentiated technology integration, and smaller form factor in complex System-on-a-Chip (SoC) design. High density vertical connections between stacked strata reduce well-known interconnect delay issues and increases interconnect bandwidth in a 3D chip. Adding the third dimension to design opens up new opportunities for EDA tools and design/architectural techniques to fully explore new approaches and address the challenges of 3D integration. This tutorial will discuss following key topics in 3D integration: -Overview of 3D integration process: Through-Si via, die-on-wafer, wafer-on-wafer bonding -Market applications and drivers for 3D integration -Design techniques for cost-effective 3D integration: 3D IP reuse, design-for-test -Thermal issues in 3D -CAD tools and algorithms for 3D IC design -3D microprocessor design -3D multi-core architectures with network-on-chip |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1366110.1366112 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
differentiated technology integration,new opportunity,cad tool,microprocessor design,design technique,ic design,3d cad,process technology,new approach,integration technology,eda tool,integration process,3d ic,three dimensional,chip,form factor,cost effectiveness,complex system,network on chip,design for test | Technology integration,Work in process,Computer science,Reuse,Electronic engineering,Electronic design automation,Bandwidth (signal processing),Three-dimensional integrated circuit,Interconnection,Technology CAD | Conference |
Citations | PageRank | References |
1 | 0.37 | 1 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Syed M. Alam | 1 | 176 | 20.47 |
| Mike Ignatowski | 2 | 192 | 11.60 |
| Yuan Xie | 3 | 6430 | 407.00 |