| Nano Magnetic STT-Logic Partitioning for Optimum Performance | 0 | 0.34 | 2014 |
| Welcome to ISQED 2013. | 0 | 0.34 | 2013 |
| ST-MRAM fundamentals, challenges, and applications | 1 | 0.43 | 2013 |
| Non-destructive variability tolerant differential read for non-volatile logic | 1 | 0.35 | 2012 |
| Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture. | 0 | 0.34 | 2012 |
| Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures. | 8 | 0.94 | 2011 |
| Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices | 0 | 0.34 | 2011 |
| Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis | 3 | 0.41 | 2011 |
| Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints | 2 | 0.42 | 2011 |
| Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies | 26 | 1.37 | 2011 |
| Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits | 31 | 2.66 | 2010 |
| Interstratum connection design considerations for cost-effective 3-D system integration | 3 | 0.86 | 2010 |
| System-Level Comparison Of Power Delivery Design For 2d And 3d Ics | 18 | 1.09 | 2009 |
| Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology | 9 | 0.55 | 2009 |
| Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis | 0 | 0.34 | 2009 |
| Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs | 12 | 1.38 | 2009 |
| Technology, CAD tools, and designs for emerging 3D integration technology | 1 | 0.37 | 2008 |
| A 180 Kbit Embeddable MRAM Memory Module | 1 | 0.75 | 2008 |
| A Built-In Self-Test Scheme for Soft Error Rate Characterization | 7 | 0.55 | 2008 |
| Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology | 20 | 2.44 | 2007 |
| Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations | 7 | 0.81 | 2007 |
| Electromigration Reliability Comparison of Cu and Al Interconnects | 7 | 1.21 | 2005 |
| Thermal aware cell-based full-chip electromigration reliability analysis | 3 | 0.67 | 2005 |
| Circuit Level Reliability Analysis of Cu Interconnects | 16 | 1.54 | 2004 |
