Name
Abstract | ||
|---|---|---|
Phase change RAM (PRAM) is a promising memory technology because of its fast read access time, high storage density and very low standby power. Multi-level Cell (MLC) PRAM which has been introduced to further improve the storage density, comes at a price of lower reliability. This paper focuses on a cost-effective solution for improving the reliability of MLC-PRAM. As the first step, we study in detail the causes of hard and soft errors and develop error models to capture these effects. Next we propose a multi-tiered approach that spans architecture, circuit and system levels to increase the reliability. At the architecture level, we use a combination of Gray code encoding and 2-bit interleaving to partition the errors so that a lower strength error correction coding (ECC) can be used for half of the bits that are in the odd block. We use sub block flipping and threshold resistance tuning to reduce the number of errors in the even block. For even higher reliability, we use a simple BCH based ECC on top of these techniques. We show that the propose multi-tiered approach enables us to use a low cost ECC with 2-error correction capability (t=2) instead of one with t=8 to achieve a block failure rate of 10-8. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SiPS.2012.46 | SiPS |
Keywords | Field | DocType |
multitiered approach,multi-level cell pram,gray codes,odd block,storage density,mlc pram,low cost ecc,memory technology,phase change memories,multilevel cell pram,multi-tiered approach,cost-effective solution,system level,error correction codes,high storage density,read access time,error models,circuit level,lower reliability,error correction coding,2-bit interleaving,ecc,multi-level cell,reliability,higher reliability,hard errors,error model,gray code encoding,phase change ram,soft errors,block failure rate,phase change memory,standby power,2-error correction capability,threshold resistance tuning,interleaved codes,architecture level,sub block flipping,concurrency theory | Multi-level cell,Access time,Standby power,Computer science,Parallel computing,Failure rate,Real-time computing,BCH code,Gray code,Computer hardware,Interleaving,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
2162-3562 | 978-1-4673-2986-6 | 3 |
PageRank | References | Authors |
0.44 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chengen Yang | 1 | 56 | 5.47 |
| Yunus Emre | 2 | 60 | 5.60 |
| Yu Cao | 3 | 2765 | 245.91 |
| Chaitali Chakrabarti | 4 | 1978 | 184.17 |