Name
Abstract | ||
|---|---|---|
We present efficient method for reducing test application time by broadcasting test configuration. We compare our method based on single, multiple, 1-1 in-order mapping, even distribution, nearest signal probability matching, and in-order pseudo-exhaustive method. The results of our experiments indicate that our method reducing the test pattern number and the test application time by running the ATPG tool provided by SIS |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692902 | ISCAS |
Keywords | DocType | ISSN |
integrated circuit testing,broadcasting test configuration,test application time,automatic test pattern generation,bist,test size,vlsi,test application time reduction,testing,very large scale integration,benchmark testing,structural testing,fault detection,broadcasting | Conference | 0271-4302 |
ISBN | Citations | PageRank |
0-7803-9389-9 | 0 | 0.34 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiann-Chyi Rau | 1 | 13 | 6.75 |
| Jun-yi Chang | 2 | 3 | 0.78 |
| Chien-shiun Chen | 3 | 12 | 1.60 |