Jiann-Chyi Rau - Citegraph

Author Info

Name	Affiliation	Papers
JIANN-CHYI RAU	Tamkang Univ, Dept Elect Engn, Tamsui 25137, Taipei County, Taiwan	19
Collaborators	Citations	PageRank
23	13	6.75
Referers	Referees	References
37	287	152

Search Limit

100287

Publications (19 rows)

Collaborators (23 rows)

Referers (37 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Compact Test Pattern Selection for Small Delay Defect	5	0.46	2013
Optimal unknown bit filtering for test response masking	0	0.34	2012
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment.	0	0.34	2011
The AB-filling methodology for power-aware at-speed scan testing	0	0.34	2010
Multi-chains encoding scheme in low-cost ATE	0	0.34	2010
New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology	1	0.37	2009
Low Power Multi-Chains Encoding Scheme For Soc In Low-Cost Environment	0	0.34	2009
Reducing switching activity by test slice difference technique for test volume compression	2	0.38	2009
The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design.	0	0.34	2008
An efficient test-data compaction for low power VLSI testing	1	0.36	2008
Design Of Dynamically Assignmentable Tam Width For Testing Core-Based Socs	0	0.34	2006
A Novel Hardware Architecture For Low Power And Rapid Testing Of Vlsi Circuits	0	0.34	2006
A broadcast-based test scheme for reducing test size and application time	0	0.34	2006
A novel reseeding mechanism for pseudo-random testing of VLSI circuits	1	0.35	2005
Reconfigurable multiple scan-chains for reducing test application time of SOCs	0	0.34	2005
An efficient low-overhead policy for constructing multiple scan-chains	3	0.44	2004
An enhanced tree-structured scan chain for pseudo-exhaustive testing of VLSI circuits	0	0.34	2003
A don't-care based image circuit for function verification	0	0.34	2002
A timing-driven pseudoexhaustive testing for VLSI circuits	0	0.34	2001

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