Paper Info
Title
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Abstract
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the high logic value, causing the pMOS transistor of the downstream buffer to not turn fully off, this approach suffers from static power consumption and reduced noise margins. The standard pMOS transistor pull-up in an active feedback of an inverter reduces the static power consumption, but degrades the switching time and/or active power consumption. We propose a circuit technique to build level-restoring buffers, which improves the propagation delay or active power consumption at a tiny area penalty. Our main idea is to replicate the nMOS element of the downstream buffer, where each replica is driven by a signal that originates from earlier stages of the nMOS-tree multiplexer. This way, when passing high logic values, signals from earlier stages directly drive the downstream buffer improving the delay or the slope of the transition edge. The passing of low logic values is still performed in the original way by the nMOS tree and the pMOS element of the downstream buffer. The simulations indicate an average improvement of the composite metric area-delay-energy product of 25% versus the standard approach across 180nm, 130nm, and 90nm technologies.
Year
DOI
Venue
2007
10.1109/DSD.2007.22
DSD
Keywords
Field
DocType
field programmable gate arrays,field programmable gate array,energy production,threshold voltage,propagation delay
Inverter,Propagation delay,NMOS logic,Computer science,Field-programmable gate array,Multiplexer,Real-time computing,Transistor,PMOS logic,AND gate
Conference
ISBN
Citations 
PageRank 
0-7695-2978-X
5
0.51
References 
Authors
10
3
Name
Order
Citations
PageRank
S. Miller1122.52
Mihai Sima29516.66
Michael McGuire3322.59