Name
Abstract | ||
|---|---|---|
Design-for-test techniques for wafer test, component test and system-level diagnostics are implemented on stand-alone SRAMs at 1Gb/s/pin. These design-for-test techniques achieve several objectives: improved tester measurement accuracy, higher component yield, and optimal system-level SRAM performance. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/TEST.2000.894235 | INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS |
Keywords | Field | DocType |
control systems,design for test,frequency,system on a chip,system testing,design for testability | Design for testing,Wafer,System on a chip,Computer science,System testing,Automatic testing,Electronic engineering,Static random-access memory,Real-time computing,Accuracy and precision,Control system,Embedded system | Conference |
ISSN | Citations | PageRank |
1089-3539 | 2 | 1.03 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Herold Pilo | 1 | 5 | 1.59 |
| Stu Hall | 2 | 2 | 1.03 |
| Patrick Hansen | 3 | 2 | 1.03 |
| Steve Lamphier | 4 | 47 | 9.38 |
| Chris Murphy | 5 | 2 | 1.03 |