Name
Abstract | ||
|---|---|---|
This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TVLSI.2006.887833 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
single-ended cdmff,differential structure,conditional capture flip-flop,differential cdmffs,power dissipation,data-to-output delay,low-power electronics,modified sense amplifier flip-flop,transmission-gate pulsed latch,conditional data mapping flip-flops,pulse-triggered flip-flops,power delay product,high-speed integrated circuits,single-ended structure,cmos digital integrated circuits,dynamic power,high-performance system,flip-flops,data activity,high-performance flip-flop,low-power integrated circuits,redundant internal transitions,timing reliability,conditional data,low power electronics,integrated circuit | Power–delay product,Dissipation,Data mapping,Computer science,FLOPS,Electronic engineering,Dynamic demand,Differential structure,Low-power electronics,Amplifier | Journal |
Volume | Issue | ISSN |
14 | 12 | 1063-8210 |
Citations | PageRank | References |
8 | 0.86 | 9 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chen Kong Teh | 1 | 39 | 4.66 |
| Mototsugu Hamada | 2 | 130 | 22.06 |
| Tetsuya Fujita | 3 | 62 | 14.04 |
| Hiroyuki Hara | 4 | 67 | 7.06 |
| Nobuyuki Ikumi | 5 | 12 | 2.57 |
| Yukihito Oowaki | 6 | 38 | 6.51 |