Name
Abstract | ||
|---|---|---|
In this paper, we examine the efficiency of the ARRIVE architecture, a coarse-grain reconfigurable datapath extension to an embedded RISC microprocessor. It is considered platform specific, optimized for the media and communication processing domain. Detailed chip area requirements are obtained through the mapping to an UMC 0.18μm standard cell ASIC process layout. Furthermore, we present hardware utilization and power simulation results of six media/communication benchmark applications based on post-layout process information. As a result, we can recognize increased area efficiency ($\frac{operations}{mm^2\cdot s}$) and power efficiency ($\frac{operations}{mW\cdot s}$) of the reconfigurable datapath extended RISC microprocessor. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-78610-8_32 | ARC |
Keywords | Field | DocType |
power efficiency,embedded risc microprocessor,area efficiency,communication processing domain,case study,post-layout process information,detailed chip area requirement,dynamic reconfigurable datapath extensions,communication benchmark application,power simulation result,coarse-grain reconfigurable datapath extension,risc microprocessor,chip | Power simulation,Electrical efficiency,Datapath,Computer science,Parallel computing,Microprocessor,Chip,Real-time computing,Application-specific integrated circuit,Standard cell,Embedded system | Conference |
Volume | ISSN | Citations |
4943 | 0302-9743 | 1 |
PageRank | References | Authors |
0.40 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Steffen Köhler | 1 | 9 | 4.26 |
| Jan Schirok | 2 | 1 | 0.40 |
| Jens Braunes | 3 | 6 | 2.34 |
| Rainer G. Spallek | 4 | 137 | 25.30 |