| A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. | 0 | 0.34 | 2017 |
| First Workshop on Hardware Defined Programming - HDP. | 0 | 0.34 | 2017 |
| Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. | 0 | 0.34 | 2017 |
| RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models | 0 | 0.34 | 2016 |
| Migration of long-running Tasks between Reconfigurable Resources using Virtualization. | 1 | 0.36 | 2016 |
| Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud | 2 | 0.37 | 2015 |
| Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. | 0 | 0.34 | 2015 |
| RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment | 3 | 0.42 | 2015 |
| Educating hardware design — From primary school children to postgraduate engineers | 0 | 0.34 | 2014 |
| PoC-align: An open-source alignment accelerator using FPGAs | 0 | 0.34 | 2014 |
| Ready PCIe data streaming solutions for FPGAs | 2 | 0.40 | 2014 |
| Superblock compilation and other optimization techniques for a Java-based DBT machine emulator | 2 | 0.36 | 2013 |
| Integration of a multi-FPGA system in a common cluster environment | 1 | 0.36 | 2013 |
| Short-Read Mapping by a Systolic Custom FPGA Computation | 5 | 0.50 | 2012 |
| Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace. | 0 | 0.34 | 2012 |
| Increasing the efficiency of an embedded multi-core bytecode processor using an object cache | 0 | 0.34 | 2012 |
| The Java Virtual Machine in retargetable, high-performance instruction set simulation | 2 | 0.41 | 2011 |
| Next-generation massively parallel short-read mapping on FPGAs | 18 | 1.56 | 2011 |
| Accelerating Computations on FPGA Carry Chains by Operand Compaction | 0 | 0.34 | 2011 |
| Solving Sudokus through an incidence matrix on an FPGA. | 1 | 0.37 | 2010 |
| Application requirements and efficiency of embedded Java bytecode multi-cores | 2 | 0.39 | 2010 |
| An embedded GC module with support for multiple mutators and weak references | 2 | 0.37 | 2010 |
| Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains | 2 | 0.41 | 2010 |
| Mapping basic prefix computations to fast carry-chain structures | 4 | 0.59 | 2009 |
| Generating the trace qualification configuration for MCDS from a high level language | 0 | 0.34 | 2009 |
| High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. | 0 | 0.34 | 2009 |
| Efficiency of Dynamic Reconfigurable Datapath Extensions --- A Case Study | 1 | 0.40 | 2008 |
| Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings | 20 | 2.07 | 2008 |
| Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor | 1 | 0.40 | 2008 |
| Enabling constant-time interface method dispatch in embedded Java processors | 3 | 0.41 | 2007 |
| Bump-pointer method caching for embedded Java processors | 14 | 0.64 | 2007 |
| Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture | 25 | 1.04 | 2007 |
| A Compiler-Oriented Architecture Description for Reconfigurable Systems | 0 | 0.34 | 2006 |
| Analysis of a Fully-Scalable Digital Fractional Clock Divider | 1 | 0.36 | 2006 |
| Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures | 1 | 0.42 | 2006 |
| Ein Zwischenformat-Profiler für das RECAST-Framework | 0 | 0.34 | 2005 |
| Design Space Exploration of Coarse-Grain Reconfigurable DSPs | 5 | 0.89 | 2005 |
| RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures | 2 | 0.46 | 2004 |
| RECAST - Design space exploration for dynamic and reconfigurable embedded computing | 0 | 0.34 | 2004 |
| Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration | 2 | 0.46 | 2004 |
| Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms | 0 | 0.34 | 2003 |
| A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor | 0 | 0.34 | 2002 |
| Improving Code Efficiency for Reconfigurable VLIW Processors | 1 | 0.35 | 2002 |
| Prototyping Framework for Reconfigurable Processors | 1 | 0.39 | 2001 |
| Formal Verification of a Reconfigurable Microprocessor | 0 | 0.34 | 2000 |
| Formal Verification for Microprocessors with Extendable Instruction Set | 1 | 0.40 | 2000 |
| Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. | 0 | 0.34 | 2000 |
| Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic | 1 | 0.43 | 1999 |
| A Concept for an Evaluation Framework for Reconfigurable Systems | 4 | 0.88 | 1999 |
| Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen | 0 | 0.34 | 1998 |
