Name
Abstract | ||
|---|---|---|
In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1st time quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1TLSB in reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6272164 | ISCAS |
Keywords | Field | DocType |
circuit reliability,cjs technique,circuit noise,jitter,auxiliary pipelined tdc,redundancy range,clocks,pipelined time-to-digital converter,time reference,redundancy,time-digital conversion,reference clock,jitter induced error,correlated jitter sampling,quantization stage,reference circuits,sndr performance,jitter cancellation,pipeline processing,capacitors,linearity,quantization,tin | Capacitor,Computer science,Circuit reliability,Linearity,Electronic engineering,Redundancy (engineering),Sampling (statistics),Jitter,Quantization (signal processing),Computer hardware,Least significant bit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-4673-0218-0 | 2 |
PageRank | References | Authors |
0.46 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Taehwan Oh | 1 | 13 | 4.85 |
| Hariprasath Venkatram | 2 | 36 | 6.72 |
| Jon Guerber | 3 | 29 | 3.83 |
| Un-Ku Moon | 4 | 836 | 140.98 |