| Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR | 0 | 0.34 | 2020 |
| A 951-fs rms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator | 0 | 0.34 | 2020 |
| An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier | 0 | 0.34 | 2019 |
| A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier | 2 | 0.37 | 2019 |
| Session 22 overview: Gigahertz data converters: Data converter subcommittee. | 0 | 0.34 | 2018 |
| A Multi-Path Ring Amplifier With Dynamic Biasing | 0 | 0.34 | 2017 |
| A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. | 0 | 0.34 | 2017 |
| A 74.33 Db Sndr 20 Msps 2.74 Mw Pipelined Adc Using A Dynamic Deadzone Ring Amplifier | 0 | 0.34 | 2017 |
| Voltage Domain Correction Technique For Timing Skew Errors In Time Interleaved Adcs | 0 | 0.34 | 2017 |
| Pseudo-pseudo-differential circuits. | 1 | 0.38 | 2017 |
| Session 16 overview: Gigahertz data converters. | 0 | 0.34 | 2017 |
| Data converter reflections: 19 papers from the last ten years that deserve a second look. | 0 | 0.34 | 2016 |
| A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS. | 0 | 0.34 | 2016 |
| A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers | 1 | 0.38 | 2016 |
| Selectable Starting Bit Sar Adc | 0 | 0.34 | 2015 |
| Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers | 1 | 0.48 | 2015 |
| A Continuous-Time ???Σ ADC Utilizing Time Information for Two Cycles Excess Loop Delay Compensation | 0 | 0.34 | 2015 |
| A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW | 1 | 0.36 | 2015 |
| A ΔΣ ADC using an LSB-first SAR quantizer | 0 | 0.34 | 2015 |
| A single OpAmp 2nd-Order ΔΣ ADC with a double integrating quantizer. | 0 | 0.34 | 2015 |
| Digitally synthesized stochastic flash ADC using only standard digital cells | 33 | 2.13 | 2014 |
| Stochastic approximation register ADC | 3 | 0.54 | 2014 |
| A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier | 2 | 0.48 | 2014 |
| Blind background calibration of harmonic distortion based on selective sampling | 1 | 0.37 | 2013 |
| Parallel gain enhancement technique for switched-capacitor circuits. | 4 | 0.73 | 2013 |
| Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End | 4 | 0.47 | 2013 |
| Little-known features of well-known creatures. | 0 | 0.34 | 2012 |
| The Effect Of Correlated Level Shifting On Noise Performance In Switched Capacitor Circuits | 0 | 0.34 | 2012 |
| Correlated jitter sampling for jitter cancellation in pipelined TDC | 2 | 0.46 | 2012 |
| Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. | 1 | 0.36 | 2012 |
| A 10-b Ternary SAR ADC With Quantization Time Information Utilization. | 14 | 0.93 | 2012 |
| The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping. | 5 | 0.62 | 2012 |
| Enhanced Sar Adc Energy Efficiency From The Early Reset Merged Capacitor Switching Algorithm | 2 | 0.62 | 2012 |
| A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers | 9 | 1.56 | 2012 |
| A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer | 3 | 0.59 | 2011 |
| A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC. | 0 | 0.34 | 2011 |
| Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. | 9 | 0.70 | 2011 |
| A 10b Ternary SAR ADC with decision time quantization based redundancy | 5 | 0.50 | 2011 |
| A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp. | 1 | 0.35 | 2011 |
| Design-Oriented Analysis of Circuits With Equality Constraints. | 0 | 0.34 | 2011 |
| An 11.1 Mw 42 Ms/S 10 B Adc With Two-Step Settling In 0.18 Mu M Cmos | 4 | 0.59 | 2010 |
| An interstage correlated double sampling technique for switched-capacitor gain stages | 3 | 0.62 | 2010 |
| A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. | 6 | 0.95 | 2010 |
| PDF folding for stochastic flash ADCs. | 1 | 0.39 | 2010 |
| Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers | 20 | 1.36 | 2009 |
| An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. | 1 | 0.39 | 2009 |
| A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver | 5 | 0.84 | 2009 |
| A multiplexer-based digital passive linear counter (PLINCO) | 0 | 0.34 | 2009 |
| Automated design and optimization of low-noise oscillators | 0 | 0.34 | 2009 |
| A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS. | 1 | 0.43 | 2009 |
