Name
Abstract | ||
|---|---|---|
In this paper, we present a low-power Distributed Arithmetic (DA) architecture. In a DA architecture, a memory is employed to store linear combinations of coefficients. The probability distribution of addresses to the memory is usually not uniform because of temporal correlation in the input. We present a rule governing this probability distribution and use it to partition the memory such that the most frequently accessed locations are stored in the smallest memory. Power dissipation is reduced because accesses to smaller memories dissipate less power. Experimental results with an 8-tap filter with 8 bits of data precision result in a 32% power reduction in the memory. A 28% power reduction was obtained by just detecting accesses to the two most frequently accessed locations (0x00 and 0xFF), which is a strong argument for using the techniques proposed in this paper. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ISCAS.1999.778885 | ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING |
Keywords | Field | DocType |
power dissipation,digital filters,distributed computing,computer architecture,arithmetic,logic,digital signal processing,probability distribution,linear combinations,fir filters,low power electronics,finite impulse response filter | Memory bank,Registered memory,Interleaved memory,Uniform memory access,Computer science,Parallel computing,Distributed memory,Electronic engineering,Probability distribution,Flat memory model,Memory architecture | Conference |
Citations | PageRank | References |
2 | 0.42 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sumant Ramprasad | 1 | 202 | 18.20 |
| Naresh R. Shanbhag | 2 | 2027 | 205.25 |
| Ibrahim N. Hajj | 3 | 572 | 79.52 |