Name
Title | ||
|---|---|---|
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS. |
Abstract | ||
|---|---|---|
This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous operation and boosted self-power gating are proposed to improve conversion accuracy and reduce static leakage power. By designing with MOSFET of high threshold voltage (HVt) and low threshold voltage (LVt), the leakage power is reduced without decrease of maximum sampling frequency. The test chip in 40-nm CMOS pr... |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2013.2274851 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Delays,MOSFET,Power demand,Leakage currents,Clocks,Switches,CMOS integrated circuits | Clock gating,Computer science,Electronic engineering,CMOS,Effective number of bits,Power gating,Low voltage,MOSFET,Electrical engineering,Switched-mode power supply,Low-power electronics | Journal |
Volume | Issue | ISSN |
48 | 11 | 0018-9200 |
Citations | PageRank | References |
16 | 1.10 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryota Sekimoto | 1 | 77 | 9.08 |
| Akira Shikata | 2 | 77 | 9.08 |
| Kentaro Yoshioka | 3 | 54 | 9.04 |
| Tadahiro Kuroda | 4 | 659 | 213.23 |
| Hiroki Ishikuro | 5 | 285 | 52.15 |