Kentaro Yoshioka - Citegraph

Author Info

Name	Affiliation	Papers
KENTARO YOSHIOKA	Hepato-Gastroenterology, School of Medicine, Fujita Health University, Fujita, Japan	20
Collaborators	Citations	PageRank
97	54	9.04
Referers	Referees	References
230	182	69

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100230

Publications (20 rows)

Collaborators (97 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Poster: Towards Large-Scale Measurement Study on LiDAR Spoofing Attacks against Object Detection	0	0.34	2022
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs	0	0.34	2021
Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections	0	0.34	2021
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE	0	0.34	2020
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE	2	0.38	2020
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits	1	0.37	2019
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.	2	0.38	2019
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.	9	0.61	2018
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications	0	0.34	2018
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.	0	0.34	2018
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators.	0	0.34	2018
An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS	4	0.54	2015
A 13b SAR ADC with eye-opening VCO based comparator	5	0.41	2014
7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique	2	0.50	2014
An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting technique	1	0.36	2014
A 4-10 Bit, 0.4-1 V Power Supply, Power Scalable Asynchronous Sar-Adc In 40 Nm-Cmos With Wide Supply Voltage Range Sar Controller	2	0.46	2013
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS.	16	1.10	2013
An Adaptive Dac Settling Waiting Time Optimized Ultra Low Voltage Asynchronous Sar Adc In 40 Nm Cmos	1	0.41	2013
Efficacy of interferon treatment for chronic hepatitis C predicted by feature subset selection and support vector machine.	1	0.38	2007
Support vector machine-based feature selection for classification of liver fibrosis grade in chronic hepatitis C.	8	0.78	2006