Name
Abstract | ||
|---|---|---|
In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR tuning mode. In FPR mode, the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement in power reduction with the FPR optimization mode. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1007/978-3-642-11802-9_35 | PATMOS |
Keywords | Field | DocType |
free power recovery,new methodology,power reduction,fpr tuning mode,fpr methodology,low power circuit design,total power,power property,power reduction result,fpr mode,einstuner circuit,fpr optimization mode,power-aware transistor sizing,circuit design,duty cycle | Leakage (electronics),Computer science,Microprocessor,Circuit design,Real-time computing,Electronic engineering,Transistor sizing,Electrical engineering | Conference |
Volume | ISSN | ISBN |
5953 | 0302-9743 | 3-642-11801-1 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Milena Vratonjic | 1 | 16 | 3.04 |
| Matthew Ziegler | 2 | 11 | 1.97 |
| George Gristede | 3 | 27 | 4.76 |
| Victor Zyuban | 4 | 233 | 22.27 |
| Thomas Mitchell | 5 | 16 | 3.81 |
| Ee Cho | 6 | 0 | 0.34 |
| Chandu Visweswariah | 7 | 615 | 60.90 |
| Vojin G. Oklobdzija | 8 | 806 | 137.25 |