| Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders | 1 | 0.38 | 2015 |
| A quick method for energy optimized gate sizing of digital circuits | 0 | 0.34 | 2011 |
| Energy efficient implementation of parallel CMOS multipliers with improved compressors | 11 | 1.16 | 2010 |
| Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010 | 78 | 9.11 | 2010 |
| Design of a link-controller architecture for multiple serial link protocols. | 0 | 0.34 | 2010 |
| Computing at the ultimate low-energy limits | 0 | 0.34 | 2010 |
| A new methodology for power-aware transistor sizing: free power recovery (FPR) | 0 | 0.34 | 2009 |
| Low-power soft error hardened latch | 2 | 0.42 | 2009 |
| Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 | 77 | 11.07 | 2008 |
| Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements | 3 | 0.48 | 2008 |
| Energy-delay space analysis for clocked storage elements under process variations | 1 | 0.42 | 2006 |
| Circuit sizing and supply-voltage selection for low-power digital circuit design | 2 | 0.45 | 2006 |
| Methodology for energy-efficient digital circuit sizing: important issues and design limitations | 2 | 0.39 | 2006 |
| Energy optimization of pipelined digital systems using circuit sizing and supply scaling | 18 | 1.17 | 2006 |
| A new model for timing jitter caused by device noise in current-mode logic frequency dividers | 0 | 0.34 | 2005 |
| Efficient Mapping of Addition Recurrence Algorithms in CMOS | 12 | 0.94 | 2005 |
| Low- and Ultra Low-Power Arithmetic Units: Design and Comparison | 9 | 1.18 | 2005 |
| Proceedings of the Third IASTED International Conference on Circuits, Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005 | 5 | 1.53 | 2005 |
| Dual-edge triggered storage elements and clocking strategy for low-power systems | 33 | 1.82 | 2005 |
| Comparison of high-performance VLSI adders in the energy-delay space | 24 | 2.04 | 2005 |
| Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs | 0 | 0.34 | 2003 |
| Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders | 22 | 1.86 | 2003 |
| Conditional pre-charge techniques for power-efficient dual-edge clocking | 8 | 0.97 | 2002 |
| Clocking and Clocked Storage Elements in Multi-GHz Environment | 0 | 0.34 | 2002 |
| Performance Comparison of VLSI Adders Using Logical Effort | 1 | 0.41 | 2002 |
| Future directions in clocking multi-ghz systems | 1 | 0.59 | 2002 |
| Comparative analysis of double-edge versus single-edge triggered clocked storage elements | 3 | 0.67 | 2002 |
| Clocked CMOS adiabatic logic with integrated single-phase power-clock supply | 27 | 2.80 | 2000 |
| Dynamic Flip-Flop with Improved Power | 12 | 1.52 | 2000 |
| Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems | 121 | 19.79 | 1999 |
| VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing | 0 | 0.34 | 1999 |
| Comparative Analysis of Latches and Flip-Flops for High-Performance Systems | 2 | 2.09 | 1998 |
| A unified approach in the analysis of latches and flip-flops for low-power systems | 12 | 8.29 | 1998 |
| Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results | 8 | 2.36 | 1997 |
| Implementing Multiply-Accumulate Operation in Multiplication Time | 12 | 1.50 | 1997 |
| Comments on "Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition" | 3 | 1.06 | 1997 |
| Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters | 11 | 2.42 | 1996 |
| A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach | 131 | 16.48 | 1996 |
| Design strategies for optimal hybrid final adders in a parallel multiplier | 21 | 2.36 | 1996 |
| Design Strategies for Optimal Multiplier Circuits | 10 | 2.39 | 1995 |
| Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology | 54 | 11.70 | 1995 |
| Monte Carlo and molecular dynamics simulations using p4 | 0 | 0.34 | 1995 |
| Multithreaded Decoupled Architecture | 10 | 0.97 | 1995 |
| Simulations Of Interacting Many Body Systems Using P4 | 1 | 0.45 | 1995 |
| An integrated multiplier for complex numbers | 9 | 2.89 | 1994 |
| High-Performance Computer Arithmetic and Implementations: Introduction | 0 | 0.34 | 1994 |
| Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming | 17 | 1.58 | 1992 |
| Improved CLA scheme with optimized delay | 6 | 2.00 | 1991 |
| Issues in CPU-coprocessor communication and synchronization | 2 | 1.36 | 1988 |
| On implementing addition in VLSI technology | 20 | 7.19 | 1988 |
