Paper Info
Title
A New Power Efficient Current-Mode 4-Pam Transmitter Interface For Off-Chip Interconnect
Abstract
In this work we propose a power-efficient 4-PAM current-mode transmitter for high-speed chip-to-chip data communication applications. The proposed transmitter meets the impedance requirements of current-mode communication. It offers high output impedance for outbound signal, a requirement of a current-mode transmitter and simultaneously provides back impedance of 100-Omega differential for reflections coming from the line. This unique feature offers significant power savings compared to a conventional 4-PAM transmitter for target signal swing. The proposed back terminated transmitter is implemented in 1.8-V, 0.18-mu m digital CMOS technology, which takes into device parasitic and second order effects. The 4-PAM transmitter able to support data rates of 10-Gb/s over a FR4 PCB trace of length 7.5-inch for a target bit-error rate(BER) of 10(-12). The industry standard 7.5-inch FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100-MHz to 20-GHz. The power consumed in the 4-PAM transmitter is 10.2-mW, this power is 37.5% lower than a conventional passive terminated current-mode 4-PAM transmitter power consumption.
Year
DOI
Venue
2010
10.1109/APCCAS.2010.5774951
PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS)
Keywords
Field
DocType
4-PAM transmitter, current-mode circuits, chip-to-chip interconnect, high-speed Circuits
Power budget,Output impedance,Transmitter,Transmitter power output,Radio frequency power transmission,Computer science,Chip,CMOS,Electronic engineering,Bandwidth (signal processing),Electrical engineering
Conference
Citations 
PageRank 
References 
0
0.34
2
Authors
2
Name
Order
Citations
PageRank
P. Vijaya Sankara Rao1113.39
Pradip Mandal28423.04