| Hybrid bidirectional transceiver for multipoint-to-multipoint signalling across on-chip global interconnects | 0 | 0.34 | 2020 |
| Switched-Capacitor Common-Mode Feedback-Based Fully Differential Operational Amplifiers And Its Usage In Implementation Of Integrators | 0 | 0.34 | 2020 |
| Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination | 0 | 0.34 | 2019 |
| Fast locking, startup-circuit free, low area, 32-phase analog DLL | 0 | 0.34 | 2019 |
| A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE | 0 | 0.34 | 2019 |
| Effect of Switched-Capacitor CMFB on the Gain of Fully Differential Op-Amp for Design of Integrators. | 0 | 0.34 | 2018 |
| Submanifolds of generalized \((k, \mu )\) -space-forms. | 0 | 0.34 | 2018 |
| Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects. | 1 | 0.35 | 2017 |
| Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects. | 2 | 0.38 | 2017 |
| A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals | 0 | 0.34 | 2016 |
| High-speed energy-efficient bi-directional transceiver for on-chip global interconnects. | 3 | 0.40 | 2015 |
| Spur Reduction In Frequency Synthesizer With An Array Of Switched Capacitors | 0 | 0.34 | 2015 |
| Prediction of reference spur in frequency synthesisers | 0 | 0.34 | 2015 |
| An unsteady analysis of arterial drug transport from half-embedded drug-eluting stent | 0 | 0.34 | 2015 |
| Spur reducing architecture of frequency synthesiser using switched capacitors. | 0 | 0.34 | 2014 |
| An approach to design and implementation of on-chip clock generator for the switched capacitor based embedded DC-DC converter. | 0 | 0.34 | 2014 |
| Modeling and design of CMOS analog circuits through hierarchical abstraction | 2 | 0.39 | 2013 |
| Design And Implementation Of An Area And Power Efficient Switched-Capacitor Based Embedded Dc-Dc Converter | 0 | 0.34 | 2012 |
| Effcient approaches to overcome non-convexity issues in analog design automation | 1 | 0.35 | 2012 |
| Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling | 3 | 0.46 | 2012 |
| A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications | 5 | 0.65 | 2012 |
| Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy | 3 | 0.39 | 2012 |
| Design of push-pull dynamic leaker circuit for a low power embedded voltage regulator | 0 | 0.34 | 2012 |
| A Fast Equation Free Iterative Approach to Analog Circuit Sizing | 1 | 0.36 | 2012 |
| Improvement of Power Efficiency and output voltage Ripple of Embedded DC-DC converters with Three Step Down ratios. | 1 | 0.41 | 2012 |
| A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination. | 1 | 0.43 | 2012 |
| Improvement Of Performance Of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded Dc-Dc Converter | 0 | 0.34 | 2012 |
| A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications | 0 | 0.34 | 2011 |
| Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing | 5 | 0.47 | 2011 |
| A geometric programming aided knowledge based approach for analog circuit synthesis and sizing | 2 | 0.39 | 2011 |
| Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect | 2 | 0.49 | 2011 |
| A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture | 1 | 0.40 | 2011 |
| Technique for the reduction of output voltage ripple of switched capacitor-based DC??DC converters. | 1 | 0.37 | 2011 |
| An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology | 8 | 0.60 | 2010 |
| A New Power Efficient Current-Mode 4-Pam Transmitter Interface For Off-Chip Interconnect | 0 | 0.34 | 2010 |
| Current-mode echo cancellation for full-duplex chip-to-chip data communication. | 0 | 0.34 | 2010 |
| Switched-Capacitor Based Buck Converter Design Using Current Limiter | 0 | 0.34 | 2009 |
| Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing | 1 | 0.39 | 2009 |
| High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect | 2 | 0.45 | 2009 |
| Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple | 1 | 0.38 | 2009 |
| An automated design approach for CMOS LDO regulators | 4 | 0.49 | 2009 |
| Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination | 2 | 0.46 | 2009 |
| A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter | 6 | 0.82 | 2008 |
| An On-Chip Voltage Regulator with Improved Load Regulation and Light Load Power Efficiency | 2 | 0.79 | 2006 |
| High voltage tolerant output buffer design for mixed voltage interfaces | 0 | 0.34 | 2005 |
| A single circuit solution for voltage sensors | 0 | 0.34 | 2005 |
| On-Chip Voltage Regulator with Improved Transient Response | 1 | 0.43 | 2005 |
| A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability | 4 | 1.03 | 2004 |
| Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation | 4 | 0.66 | 2004 |
| A Narrow Pulse- Suppressing Filter For Input Buffer | 1 | 0.37 | 2004 |
