Name
Title | ||
|---|---|---|
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques |
Abstract | ||
|---|---|---|
A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-/spl mu/m n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the freq... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/4.902767 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Clocks,Delay,Circuits,Frequency synchronization,Wires,CMOS process,Jitter,Coaxial cables,Power dissipation,Data processing | Journal | 36 |
Issue | ISSN | Citations |
2 | 0018-9200 | 14 |
PageRank | References | Authors |
1.35 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yuan Yang | 1 | 227 | 36.15 |
| Shen-Iuan Liu | 2 | 1378 | 200.41 |