Name
Abstract | ||
|---|---|---|
When low threshold voltage (Vt) is applied to domino logic to improve the performance, the tradeoff between performance and noise margin is a major design issue. To resolve the tradeoff we propose Skew-Tolerant High-Speed (STHS) domino logic, which incorporates a dual keeper structure and delay logic gates. Detailed timing analysis of STHS domino logic induces optimal timing conditions wherein contention-free skew-tolerant window is maximized. We show that dual keeper structure increases innate noise-tolerance, and clock delay control logic fortifies signal skew-tolerance. Simulation results show that STHS domino logic is more robust to noise and signal skew than High-Speed (HS) domino logic, while presenting better performance and power efficiency |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISVLSI.2002.1016871 | ISVLSI |
Keywords | Field | DocType |
delay logic gate,sths,logic simulation,signal skew,power efficiency,sths domino logic,domino logic,dual keeper structure,optimal timing condition,mos logic circuits,timing,noise margin,high-speed integrated circuits,better performance,vlsi,integrated circuit noise,detailed timing analysis,threshold voltage,skew-tolerant high-speed domino logic,contention-free skew-tolerant window,optimal timing,timing analysis,logic gates,skew-tolerant high-speed,delay logic gates,clock delay control logic,circuit simulation,very large scale integration,logic gate,degradation,strontium | Domino logic,Logic gate,Sequential logic,Pass transistor logic,Computer science,Logic optimization,Electronic engineering,Logic simulation,Logic level,Control logic | Conference |
ISSN | Citations | PageRank |
2159-3469 | 1 | 0.36 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seong-ook Jung | 1 | 332 | 53.74 |
| Ki-wook Kim | 2 | 98 | 15.76 |
| Sung-Mo Steve Kang | 3 | 1198 | 213.14 |