Name
Abstract | ||
|---|---|---|
The computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000's. It was hoped that the continuous improvement of single-program performance could be achieved through these architectures. However, traditional parallelizing compilers often fail to effectively parallelize general-purpose applications which typically have complex control flow and excessive pointer usage. Recently hardware techniques such as Transactional Memory (TM) and Thread-Level Speculation (TLS) have been proposed to simplify the task of parallelization by using speculative threads. Potential of speculative parallelism in general-purpose applications like SPEC CPU 2000 have been well studied and shown to be moderately successful. Preliminary work examining the potential parallelism in SPEC2006 deployed parallel threads with a restrictive TLS execution model and limited compiler support, and thus only showed limited performance potential. In this paper, we first analyze the cross-iteration dependence behavior of SPEC 2006 benchmarks and show that more parallelism potential is available in SPEC 2006 benchmarks, comparing to SPEC2000. We further use a state-of-the-art profile-driven TLS compiler to identify loops that can be speculatively parallelized. Overall, we found that with optimal loop selection we can potentially achieve an average speedup of 60% on four cores over what could be achieved by a traditional parallelizing compiler such as Intel's ICC compiler.We also found that an additional 11% improvement can be potentially obtained on selected benchmarks using 8 cores when we extend TLS on multiple loop levels as opposed to restricting to a single loop level. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISPASS.2009.4919640 | Boston, MA |
Keywords | Field | DocType |
multiprocessing systems,parallel processing,parallelising compilers,program control structures,TLS execution model,Thread-Level Speculation,Transactional Memory,complex control flow,computer industry,multicore architectures,multithreaded architectures,optimal loop selection,parallel threads,parallelizing compilers,profile-driven TLS compiler,single-program performance,speculative parallelism,speculative threads | Instruction-level parallelism,Task parallelism,Computer science,Parallel computing,Speculative multithreading,Real-time computing,Compiler,Transactional memory,Execution model,Benchmark (computing),Speedup | Conference |
ISBN | Citations | PageRank |
978-1-4244-4184-6 | 10 | 0.55 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Venkatesan Packirisamy | 1 | 41 | 2.04 |
| Antonia Zhai | 2 | 459 | 23.62 |
| Wei-Chung Hsu | 3 | 719 | 58.87 |
| Pen-Chung Yew | 4 | 1430 | 133.52 |
| Tin-Fook Ngai | 5 | 240 | 23.07 |