Name
Abstract | ||
|---|---|---|
This paper proposes a new pipelined analog to digital converter (ADC) based on second-generation current conveyors (CCII). Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifiers (OA). Simulation results show that the proposed CCII-based pipelined ADC can work at 10 MHz with an 8-bit resolution. The DNL is within -0.4 LSB and 0.5 LSB and INL is within -0.4 LSB and 0.7 LSB, respectively. The ADC is realized in TSMC 0.35 μm CMOS technology and consumed 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm2. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1466049 | ISCAS (6) |
Keywords | Field | DocType |
tsmc cmos technology,cmos integrated circuits,0.35 micron,sample-and-hold circuit,analogue-digital conversion,multiplying digital-to-analog converter,29 mw,multiplying circuits,adc,second-generation current conveyors,ccii,s/h circuit,mdac,3.3 v,sample and hold circuits,digital-analogue conversion,current conveyors,pipelined analog to digital converter,pipeline processing,cmos technology,sample and hold circuit,digital signal processing,operational amplifiers,error correction,operational amplifier,current conveyor | Digital signal processing,Computer science,Analog-to-digital converter,Error detection and correction,CMOS,Electronic engineering,Sample and hold,Energy consumption,Electrical engineering,Operational amplifier,Least significant bit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 1 |
PageRank | References | Authors |
0.41 | 2 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuh-Shyan Hwang | 1 | 137 | 29.85 |
| Lu-po Liao | 2 | 1 | 0.41 |
| Chia-chun Tsai | 3 | 109 | 23.04 |
| Wen-Ta Lee | 4 | 16 | 5.45 |
| Trong-yen Lee | 5 | 98 | 20.70 |
| Jiann-Jong Chen | 6 | 124 | 24.08 |