Name
Title | ||
|---|---|---|
Optimal buffered routing path constructions for single and multiple clock domain systems |
Abstract | ||
|---|---|---|
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently clocked components. This paper explores simultaneous routing and buffer insertion in the context of single and multiple clock domains. We present optimal and efficient polynomial algorithms that can be used to estimate communication overhead for interconnect and resource planning in single and multi-clock domain systems. Experimental results verify the correctness and practicality of our approach. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/774572.774609 | ICCAD |
Keywords | Field | DocType |
optimal buffered routing path,cross-chip routing,multiple clock domain,buffer insertion,efficient polynomial algorithm,ip component,multiple clock domain system,clocked component,multiple clock cycle,simultaneous routing,communication overhead,soc design,assembly language,fpga,synchronisation,system on chip,integrated circuit layout,vlsi,network routing,chip,codesign,capacitance | Link-state routing protocol,Multipath routing,Equal-cost multi-path routing,Dynamic Source Routing,Static routing,Computer science,Parallel computing,Destination-Sequenced Distance Vector routing,Routing domain,Real-time computing,Electronic engineering,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1092-3152 | 0-7803-7607-2 | 30 |
PageRank | References | Authors |
1.55 | 13 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Soha Hassoun | 1 | 535 | 241.27 |
| C. J. Alpert | 2 | 2445 | 226.04 |
| Meera Thiagarajan | 3 | 30 | 1.55 |