Paper Info
Title
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
Abstract
Many of the pins on a modern chip are used for power delivery. If fewer pins were used to supply the same current, the wires and pins used for power delivery would have to carry larger currents over longer distances. This results in an "IR-drop" problem, where some of the voltage is dropped across the long resistive wires making up the power delivery network, and the eventual circuits experience fluctuations in their supplied voltage. The same problem also manifests if the pin count is the same, but the current draw is higher. IR-drop can be especially problematic in 3D DRAM devices because (i) low cost (few pins and TSVs) is a high priority, (ii) 3D-stacking increases current draw within the package without providing proportionate room for more pins, and (iii) TSVs add to the resistance of the power delivery network. This paper is the first to characterize the relationship between the power delivery network and the maximum supported activity in a 3D-stacked DRAM memory device. The design of the power delivery network determines if some banks can handle less activity than others. It also determines the combinations of bank activities that are permissible. Both of these attributes can feed into architectural policies. For example, if some banks can handle more activities than others, the architecture benefits by placing data from high-priority threads or data from frequently accessed pages into those banks. The memory controller can also derive higher performance if it schedules requests to specific combinations of banks that do not violate the IR-drop constraint. We first define an IR-drop-aware scheduler that encodes a number of activity constraints. This scheduler, however, falls short of the performance of an unrealistic ideal PDN that imposes no scheduling constraints by 4.6x. By addressing starvation phenomena in the scheduler, the gap is reduced to only 1.47x. Finally, by adding a dynamic page placement policy, performance is within 1.2x of the unrealistic ideal PDN. We thus show that architectural polices can help mitigate the limitations imposed by a cost constrained design.
Year
DOI
Venue
2013
10.1145/2540708.2540726
MICRO
Keywords
Field
DocType
memory device,higher performance,ir-drop-aware scheduler,architectural policy,activity constraint,increases current draw,current draw,power delivery,bank activity,ir-drop constraint,power delivery network,unrealistic ideal pdn,ir drop
Dram,Power network design,Computer science,Scheduling (computing),Parallel computing,Thread (computing),Real-time computing,Chip,Schedule,Electronic circuit,Memory controller
Conference
ISBN
Citations 
PageRank 
978-1-5090-6603-2
26
0.84
References 
Authors
25
6
Name
Order
Citations
PageRank
Manjunath Shevgoor11083.92
Jung-Sik Kim213811.69
Niladrish Chatterjee326711.53
Rajeev Balasubramonian42302116.79
Al Davis598654.47
Aniruddha N. Udipi61505.94