| Practical and efficient incremental adaptive routing for HyperX networks | 1 | 0.37 | 2019 |
| SuperSim: Extensible Flit-Level Simulation of Large-Scale Interconnection Networks | 0 | 0.34 | 2018 |
| A unified memory network architecture for in-memory computing in commodity servers. | 1 | 0.36 | 2016 |
| Memory Considerations for Low Energy Ray Tracing | 6 | 0.45 | 2015 |
| NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads | 56 | 1.34 | 2014 |
| An energy and bandwidth efficient ray tracing architecture | 17 | 0.71 | 2013 |
| Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device | 26 | 0.84 | 2013 |
| Managing Data Placement in Memory Systems with Multiple Memory Controllers. | 2 | 0.36 | 2012 |
| Staged Reads: Mitigating the impact of DRAM writes on DRAM reads | 26 | 0.96 | 2012 |
| The role of photonics in future data centers | 0 | 0.34 | 2012 |
| Optical High Radix Switch Design | 0 | 0.34 | 2012 |
| Fast, effective BVH updates for animated scenes | 18 | 0.78 | 2012 |
| LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems | 45 | 1.66 | 2012 |
| The role of optics in future high radix switch design | 34 | 1.70 | 2011 |
| Asynchronous FUD | 0 | 0.34 | 2011 |
| Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems | 38 | 1.68 | 2011 |
| Modeling NoC traffic locality and energy consumption with rent's communication probability distribution | 12 | 0.64 | 2010 |
| Handling the problems and opportunities posed by multiple on-chip memory controllers | 76 | 2.50 | 2010 |
| HyperX: topology, routing, and packaging of efficient large-scale networks | 89 | 4.94 | 2009 |
| Corona: System Implications of Emerging Nanophotonic Technology | 293 | 13.52 | 2008 |
| Application driven embedded system design: a face recognition case study | 1 | 0.35 | 2007 |
| Correct Embedded Computing Futures | 0 | 0.34 | 2004 |
| A loop accelerator for low power embedded VLIW processors | 22 | 1.57 | 2004 |
| Energy efficient cluster co-processors [3G wireless applications]. | 0 | 0.34 | 2004 |
| A low power architecture for embedded perception | 8 | 0.61 | 2004 |
| A low-power accelerator for the SPHINX 3 speech recognition system | 27 | 2.64 | 2003 |
| Perception Coprocessors for Embedded Systems | 4 | 0.91 | 2003 |
| Profiling I/O Interrupts in Modern Architectures | 3 | 0.43 | 2000 |
| Design of a Parallel Vector Access Unit for SDRAM Memory Systems | 33 | 2.43 | 2000 |
| Algorithmic foundations for a parallel vector access memory system | 6 | 0.45 | 2000 |
| Impulse: Building a Smarter Memory Controller | 126 | 7.78 | 1999 |
| Improving I/O performance with a conditional store buffer | 5 | 0.63 | 1998 |
| Memory System Support for Irregular Applications | 4 | 0.89 | 1998 |
| Efficient Communication Mechanisms for Cluster Based Parallel Computing | 7 | 0.61 | 1997 |
| Components of congestion control | 0 | 0.34 | 1996 |
