Name
Abstract | ||
|---|---|---|
Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ETSYM.2010.5512784 | European Test Symposium |
Keywords | Field | DocType |
test,diagnosis,multicore chips,microprocessor chips,pipelined test access mechanism,multicore architecture,advanced encryption standard cores,computation intensive chips,test access mechanism,scalable test architecture,array testing,multiprocessing systems,multi-core,computer architecture,pipeline processing,hardware,advanced encryption standard,chip,multi core,registers,pipelines,broadcasting,testing,cryptography,scalability | Computer architecture,Architecture,Pipeline transport,Computer science,Advanced Encryption Standard,Chip,Multicore architecture,Multi-core processor,Scalability,Embedded system | Conference |
ISSN | ISBN | Citations |
1530-1877 E-ISBN : 978-1-4244-5833-2 | 978-1-4244-5833-2 | 2 |
PageRank | References | Authors |
0.46 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chun-Chuan Chi | 1 | 117 | 8.81 |
| Wu, Cheng-Wen | 2 | 1843 | 170.44 |
| Jin-Fu Li | 3 | 662 | 59.17 |